/*
 * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
 *
 * SPDX-License-Identifier: MIT
 */

#ifndef __SAMA7G5EK_H__
#define __SAMA7G5EK_H__

#define AT91C_BASE_DDRCS 0x60000000

#ifdef CONFIG_FLEXCOM
#include "flexcom.h"
#endif

#define BOARD_PRESCALER_CPUPLL	(AT91C_PMC_PRES_CLK | \
				AT91C_PMC_CSS_CPUPLL_CLK)

#define BOARD_PRESCALER_MCK1	(AT91C_MCR_MASTER_DIV2 | \
				AT91C_MCR_CSS_SYSPLL_CLK | \
				AT91C_MCR_EN)

#define BOARD_PRESCALER_MCK1_CLEAN	(AT91C_MCR_MASTER_DIV4 | \
					AT91C_MCR_CSS_MAIN_CLK | \
					AT91C_MCR_EN)

#define BOARD_PRESCALER_MCK2	(AT91C_MCR_MASTER_DIV1 | \
				AT91C_MCR_CSS_DDRPLL_CLK | \
				AT91C_MCR_EN)

#define BOARD_PRESCALER_MCK3	(AT91C_MCR_MASTER_DIV1 | \
				AT91C_MCR_CSS_IMGPLL_CLK | \
				AT91C_MCR_EN)

#define BOARD_PRESCALER_MCK4	(AT91C_MCR_MASTER_DIV1 | \
				AT91C_MCR_CSS_SYSPLL_CLK | \
				AT91C_MCR_EN)

#define BOARD_PRESCALER_MCK4_CLEAN	(AT91C_MCR_MASTER_DIV4 | \
					AT91C_MCR_CSS_MAIN_CLK | \
					AT91C_MCR_EN)

#define MASTER_CLOCK			200000000
#define BOARD_MAINOSC			24000000

#define CONFIG_SYS_BASE_TZC400		AT91C_BASE_TZC400
#define TZC400_BASE			CONFIG_SYS_BASE_TZC400

#define CONFIG_SYS_BASE_PUBL		AT91C_BASE_PUBL
#define CONFIG_SYS_BASE_UMCTL2		AT91C_BASE_UMCTL2
#define CONFIG_SYS_BASE_UMCTL2_MP	AT91C_BASE_UMCTL2_MP

#if defined(CONFIG_SDHC0)
#define CONFIG_SYS_BASE_SDHC		AT91C_BASE_SDMMC0
#define	CONFIG_SYS_ID_SDHC		AT91C_ID_SDMMC0
#elif defined(CONFIG_SDHC1)
#define CONFIG_SYS_BASE_SDHC		AT91C_BASE_SDMMC1
#define	CONFIG_SYS_ID_SDHC		AT91C_ID_SDMMC1
#endif

#define CONFIG_SYS_SPI_CLOCK		AT91C_SPI_CLK
#define CONFIG_SYS_SPI_MODE		SPI_MODE0

#if defined(CONFIG_QSPI)
#if CONFIG_QSPI_BUS == 0
#define	CONFIG_SYS_BASE_QSPI		AT91C_BASE_QSPI0
#define	CONFIG_SYS_BASE_QSPI_MEM	AT91C_BASE_QSPI0_MEM
#define CONFIG_SYS_QSPI_MEM_SIZE	AT91C_QSPI0_MEM_SIZE
#define	CONFIG_SYS_ID_QSPI		AT91C_ID_QSPI0

#elif CONFIG_QSPI_BUS == 1
#define	CONFIG_SYS_BASE_QSPI		AT91C_BASE_QSPI1
#define	CONFIG_SYS_BASE_QSPI_MEM	AT91C_BASE_QSPI1_MEM
#define CONFIG_SYS_QSPI_MEM_SIZE	AT91C_QSPI1_MEM_SIZE
#define	CONFIG_SYS_ID_QSPI		AT91C_ID_QSPI1
#else
#error "Invalid QSPI BUS was chosen"
#endif
#endif /* CONFIG_QSPI */

/*
 * NandFlash Settings
 */
#ifdef CONFIG_NANDFLASH
#define CONFIG_SYS_NAND_BASE            AT91C_BASE_CS3
#define CONFIG_SYS_NAND_MASK_ALE        (1 << 21)
#define CONFIG_SYS_NAND_MASK_CLE        (1 << 22)
#define CONFIG_SYS_NAND_OE_PIN		AT91C_PIN_PD(6)
#define CONFIG_SYS_NAND_WE_PIN		AT91C_PIN_PD(5)
#define CONFIG_SYS_NAND_ALE_PIN		AT91C_PIN_PD(7)
#define CONFIG_SYS_NAND_CLE_PIN		AT91C_PIN_PD(8)
#define CONFIG_SYS_NAND_ENABLE_PIN      AT91C_PIN_PD(4)
#endif /* CONFIG_NANDFLASH */

#endif
